Search - stopwatch vhdl

[uCOS] Second

Description: second.rar 这个做的是一秒表计时程序，是用FPGA写的，里面代码完整，并带有文档报告-second.rar this is the one to do stopwatch timing procedures, FPGA is written inside the code integrity, and with the report document
Platform: | Size: 445440 | Author: 李天顺 | Hits:

[VHDL-FPGA-Verilog] dianzishezhong

Description: 电子时钟 EDA 基本要求： 24小时计数显示；具有校时功能（时，分）附加要求 1、秒表功能（复位，计时-Electronic clock EDA basic requirements: a 24-hour count showed with a school function (hours, minutes,) Additional requirement 1, stopwatch functions (reset, clock
Platform: | Size: 3072 | Author: Jaman | Hits:

[VHDL-FPGA-Verilog] vhdl_miaobiao

Description: 用vhdl实现秒表的功能，具有秒表功能,有分、秒显示，后期可以自己添加闹钟的模块。 -Use VHDL to achieve the functions of a stopwatch with a stopwatch function, who, seconds indicates that the latter can add their own alarm clock module.
Platform: | Size: 3072 | Author: 佘斌 | Hits:

[Other] CLOCK

Description: 文通过ALTERA公司的quartus II软件，用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为：计时功能，24小时制计时显示；通过七段数码管动态显示时间；校时设置功能，可分别设置时、分、秒；跑表的启动、停止、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital clock. The main function of the completion are: time function, 24-hour time display through the Seven-Segment LED dynamic display time school settings function, can be set hours, minutes, seconds the stopwatch to start, stop, and maintain display and removal.
Platform: | Size: 182272 | Author: 张保平 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 1 8位加法器的设计 2 分频电路 3 数字秒表的设计-1 8 adder design of 2-circuit design of 3 digital stopwatch
Platform: | Size: 569344 | Author: dai | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 基于VHDL环境下的秒表设计源代码很好用的-Environment based on VHDL design source code stopwatch good use
Platform: | Size: 1024 | Author: Jim | Hits:

[VHDL-FPGA-Verilog] run_watch

Description: 提供一个数字秒表的EDA设计实例，内故有VHDL源代码，并有运行仿真图。-To provide a digital stopwatch the EDA design example, it is within the VHDL source code, and run the simulation of Fig.
Platform: | Size: 61440 | Author: 靳朝 | Hits:

[Multimedia Develop] PlayDemo

Description: VC写的h.264规范解码程序，具体看程序注释-VC norms h.264 decoding written procedures, specific procedures see Notes
Platform: | Size: 1953792 | Author: aleckzhou | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: 基于fpga的停表设计vudl编写，使用vhdl编写的.v文件。-the stopwatch based on fpga written with vhdl
Platform: | Size: 1024 | Author: youngbing | Hits:

[Software Engineering] KESHE

Description: 基于FPGS的数字秒表设计文件含有计时，停止，复位，清零功能-FPGS-based digital stopwatch design document contains a time, stop, reset, Clear Function
Platform: | Size: 295936 | Author: 豆豆 | Hits:

[VHDL-FPGA-Verilog] VHDL312vh6

Description: 包含若干个VHDL小例子，有交通灯，电子琴，简易秒表，等等，交通灯已经测试过，根据自己的需要，稍微改动，很好用！-VHDL contains a number of small example, there is traffic lights, Electronic organ, simple stopwatch, and so on, traffic lights have been tested, according to their own needs, slightly altered, very good use!
Platform: | Size: 327680 | Author: lee gilbert | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: 一个基于FPGA的数字跑表系统的设计，最小单位是百分表位。采用十进制进位。-FPGA-based digital stopwatch system design, the smallest unit is a digital dial indicator. Binary using the metric system.
Platform: | Size: 44032 | Author: jyb | Hits:

[Other] sheji2

Description: 一个秒表的硬件设计，学习数字电路中基本RS触发器、单稳态触发器、时钟发生器及计数、译码显示等单元电路的综合应用。-The hardware design of a stopwatch, learn basic digital circuit in the RS flip-flops, monostable multivibrator, the clock generator and counting, decoding display unit integrated circuit applications.
Platform: | Size: 131072 | Author: 周妮 | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: 一个用VHDL编写的秒表程序，可用Max+PlusII仿真-Prepared by a stopwatch with VHDL procedures, Max+ PlusII simulation can be used
Platform: | Size: 620544 | Author: jiangshengcheng | Hits:

[Education soft system] Stopwatchprecisiondesign

Description: 高精度秒表设计，VHDL语言设计，课程设计，word版-Stopwatch precision design, VHDL language design, curriculum design, word version
Platform: | Size: 5120 | Author: hekan | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 秒表功能，自带工程，EDA的设计平台QuartusⅡ-Stopwatch functions, bring their own works
Platform: | Size: 1589248 | Author: huliyan | Hits:

[VHDL-FPGA-Verilog] VHDlclock

Description: 数字秒表的VHDL课程设计通过硬件测试精确到ms 最大可计时为24小时 -Digital stopwatch curriculum design through the VHDL hardware testing is accurate to ms maximum time of 24 hours
Platform: | Size: 436224 | Author: li | Hits:

[SCM] watch

Description: VHDL编写的秒表，经过试验了，用的应该还可以-VHDL stopwatch prepared, tested, and can be used
Platform: | Size: 164864 | Author: wangzw | Hits:

[VHDL-FPGA-Verilog] EXP4_sec

Description: 秒表 4个7数码管中的任何一个显示任意按键按下的次数。初始值为0，当计数到9时，下一次数值为0。利用Verilog HDL语言，编程实现上述功能。-Stopwatch
Platform: | Size: 504832 | Author: dsds | Hits:

[Embeded-SCM Develop] Multichanneldataacquisition

Description: 多路数据采集，包括八路数据模拟电压测量，计数器，99秒马表-Multi-channel data acquisition, including the eight-way analog voltage measurement data, counters, 99 seconds stopwatch
Platform: | Size: 133120 | Author: 王宇坤 | Hits:

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[uCOS] Second

[VHDL-FPGA-Verilog] dianzishezhong

[VHDL-FPGA-Verilog] vhdl_miaobiao

[Other] CLOCK

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] miaobiao

[VHDL-FPGA-Verilog] run_watch

[Multimedia Develop] PlayDemo

[VHDL-FPGA-Verilog] stopwatch

[Software Engineering] KESHE

[VHDL-FPGA-Verilog] VHDL312vh6

[VHDL-FPGA-Verilog] paobiao

[Other] sheji2

[VHDL-FPGA-Verilog] stopwatch

[Education soft system] Stopwatchprecisiondesign

[VHDL-FPGA-Verilog] miaobiao

[VHDL-FPGA-Verilog] VHDlclock

[SCM] watch

[VHDL-FPGA-Verilog] EXP4_sec

[Embeded-SCM Develop] Multichanneldataacquisition

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